1. Field of the Invention
The invention relates to a liquid crystal display module, more particularly to a method for controlling a liquid crystal display (LCD) module to show interlaced picture data thereon.
2. Description of the Related Art
A sequential scanning system is employed in the monitors of conventional personal computers. Referring to FIG. 1, scanning starts at the upper left hand corner of the monitor and moves toward the right along a nearly horizontal first line. At the end of the first line, a quick return is made to the left-hand side to start the scanning of a succeeding line, again moving toward the right. When all lines have been scanned in this way, from top to bottom, the process is repeated by returning quickly to the upper left-hand corner. Usually, a 60 Hz frame rate is employed. A main drawback of the sequential scanning system is that the resolution cannot be effectively increased.
Another type of scanning system is employed in conventional television sets. In an interlaced scanning system, odd-numbered lines are scanned first, and the even-numbered lines are scanned next. Thus, a single picture data frame consists of odd and even fields. Referring to FIG. 2, the scanning process begins at the upper left hand corner of the television screen and moves toward the right along a nearly horizontal first odd line. At the end of the first odd line, a quick return is made to the left-hand side to start the scanning of a succeeding odd line, again moving toward the right. Scanning of the odd field ends at the middle bottom of the screen. The scanning process is continued by moving quickly the scanning beam to the top center of the television screen during a vertical retrace interval to initiate scanning of the even field. When scanning the even field, the scanning process moves toward the right along a nearly horizontal first even line. At the end of the first even line, a quick return is made to the left-hand side to start the scanning of a succeeding even line, again moving toward the right. Note that the lines of the even field fall between the lines of the odd field. Scanning of the even field ends at the lower right corner of the television screen.
The interlaced scanning system permits a lower display clock rate while achieving a higher resolution. The frame rate for the interlaced scanning system is reduced to 30 Hz.
Referring to FIG. 3, a conventional LCD system is shown to comprise a central processing unit (CPU) 8, a display controller 9, a display memory 10 and an LCD module 11. The CPU 8 sends picture data to the display controller 9 for storage in the display memory 10. When it is desired to show the picture data on the LCD module 11, the display controller 9 retrieves the data from the display memory 10 and provides the same to the LCD module 11. The display controller 9 generates a shift clock signal, a line clock signal and a frame start signal to the LCD module 11 in order to control the display of the picture data on the LCD module 11.
Conventional LCD modules use a sequential scanning system instead of an interlaced scanning system. Referring to FIG. 4, a conventional 640.times.480 twin-panel LCD module includes upper and lower LCD panels 12, 13. Referring to FIG. 5, a pixel clock signal 14, a shift clock signal 15, a line clock signal 16 and a frame start signal 17 are used to control the viewing of picture data on the LCD module. A shift clock pulse (SC1, SC2, SC3, . . . SC160) is generated during the duration of four pixel clock pulses (D0, D1, D2, D3, . . . D636, D637, D638, D639). Four pixels of picture data have been sent at this stage. Each pixel of picture data may include a number of bits to indicate the tone and color of the same. A line clock pulse (LC1, . . . LC240) is generated after one hundred and sixty shift clock pulses (SC1, SC2, SC3, . . . SC160) have been generated in order to control latching of one line of picture data. In the conventional twin-panel LCD module, picture data is shown simultaneously on the upper and lower LCD panels 12, 13 of the LCD module. The upper and lower LCD panels 12, 13 require two hundred and forty lines of picture data to constitute one frame of picture data. Each line of the upper and lower LCD panels 12, 13 thus has a display duty ratio of 1/240. A frame start pulse (FP1) is then generated after two hundred and forty line clock pulses (LC1, . . . L240) in order to clear the line clock counter (not shown) of the LCD module. The frame start pulse (FP1) permits the first lines of upper and lower picture data to appear respectively on the first lines of the upper and lower LCD panels 12, 13.
The following problems are usually encountered if an interlaced scanning system is applied to the above described conventional LCD module:
1. Because the conventional LCD module is adapted for use in a sequential scanning system, picture distortion occurs if an interlaced picture data is applied to the conventional LCD module. If interlaced picture data was applied, the picture data is compressed and is shown on the upper and lower LCD panels 12, 13 of the conventional twin-panel LCD module. Interlacing of the odd and even fields does not occur, thereby resulting in picture distortion and in the generation of flickers.
2. Since the frame start pulse (FP1) permits the first lines of upper and lower picture data to appear respectively on the first lines of the upper and lower LCD panels 12, 13 of the LCD module regardless of whether the picture data constitute the odd or even fields of one frame of picture data, the odd and even data fields are shown on the same lines of the upper and lower LCD panels 12, 13, thereby resulting in flickers.